Javier Carnero (male) holds a Master degree in Computational Mathematics from the University of Seville (US), as well as a Computer Science degree in in the same university. For more than ten years, he has been participating and leading a wide range of projects in the public and private sector in different companies, as well as doing research in the computational mathematics department (US). Those projects have supposed the design and development, from complex web applications, through client-server types, to embedded devices and industrial machinery firmware. In Atos Research & Innovation (ARI) Javier is currently the principal software architect in the Advance Parallel Computing Lab, focusing on High Performance Computers (HPC). Presently he is designing the architecture within the MSO4SC project (an HPC-Cloud hybrid project), enabling a federated HPC&Cloud platform for heterogeneous executions.

Paul Carpenter received BA and MA Mathematics and MA Diploma in Computer Science from the University of Cambridge, and he received his PhD from the Technical University of Catalonia. Prior to starting his PhD, he was Senior Software Engineer at ARM and technical lead for audio/video software codecs. At BSC, he is leading the group on microserver architectures and system software. He is co-chair of the ETP4HPC Working Group on programming models, and PI of the EUROSERVER, ExaNoDe and EuroEXA projects. He is first author on three international granted patents. His research interests include programming models, system software, and energy-efficient architectures.

Fabrizio Gagliardi, born in Pisa, Italy, is Europe, Middle East and Africa Director for External Research at Microsoft Research Corporation.

He joined Microsoft in November 2005 after a long career at CERN, the world leader laboratory for particle physics in Geneva, Switzerland. There he held several technical and managerial positions since 1975: Director of the EU Grid project EGEE (2004-2005); Director of the EU Data-Grid project (2001-2004); head of mass storage services (1997-2000); Leader of the EU project GPMIMD2 (1993-1996).

Fabrizio Gagliardi has worked with four different Nobel Prize winners while at CERN. He has a Doctor degree in Computer Science, granted by the University of Pisa in 1974. Dr. Gagliardi is co-founder and member of the International Advisory Committee of the Open Grid Forum. Dr. Gagliardi has been consulting on computing and computing policy matters with the Commission of the European Union, several government and international bodies (among them NSF, DoE in the US, CNRS and other research bodies in France, EPSRC in the UK, CNR and INFN in Italy, OECD, UN agencies).

Dr. Gagliardi is author and co-author of several publications and articles on real-time and distributed computing.

Xavier Salazar joined the BSC in 2011 after several years as innovation, project manager and business developer in both industry and public sectors to provide project management support for research groups in Computer Sciences Department and manage the portfolio of HR external grants and fellowships of the centre. He has managed more than 20 FP7, H2020 and national projects, highlighting 2 coordinated projects and the management of BSC’s involvement in strategic projects such as HiPEAC Network of Excellence and the CSA Eurolab4HPC. He holds a degree in Electrical Engineering by UPC and an MSc in Economics of Innovation by Chalmers University and has been Local Chapter Coordinator of UNITECH Alumni and organizer of Telecommunications jobfair at UPC.

Dr Denis Dutoit joined CEA-Leti in 2009, after working for STMicroelectronics and STEricsson. In CEA-Leti, he has been involved in System-on-a-Chip architecture for computing and 3D Integrated Circuit projects; he has been the lead architect of several designs all combining low power, 3D integration, many core architecture and Network-on-Chip. He is now strategic marketing manager in charge of defining the Leti’s roadmap of technologies and solutions for advanced computing. He has been involved in various European research projects such as ARTIST4G, BeFEMTO, Mont-Blanc 1&2, MB2020 and he currently coordinates the ExaNoDe European collaborative project (H2020 FETHPC) developing core technologies for Exascale compute node. Dr. Dutoit holds an engineering degree from the École Nationale Supérieure d’Électronique et de Radioélectricité de Grenoble, and a Ph.D. in signal processing from the École Nationale Supérieure des Télécommunications de Paris.

Dr. Thierry Goubier (male) is a senior expert at CEA, technical lead of the heterogeneous high performance embedded computing thematic in the LCE laboratory. He is a telecommunication engineer with a PhD in graphical user interface software architectures and has been involved (sometimes as a WP leader) in numerous activities and european projects, starting in 1998, and more recently the Kalray MPPA technology transfert from CEA, the COBRA, MACH, M2DC, PROBANT, EMC2, PRODUCTIVE 4.0, and the upcoming LEXIS and European Processor Initiative. He is involved in the Software Engineering group of the ETP4HPC organisation, and interested in heterogeneous architectures, programming models, and software artefacts analysis & evolution.

Jean-Marc Philippe, Ph.D., is the Deputy Head of the Computing and Design Environment Laboratory at List, CEA Tech institute, and a researcher in the field of embedded parallel architectures. He received his PhD degree in computer engineering from the University of Rennes I, France, in 2005. He worked as a WP leader in the FP6 FET AETHER project dedicated to study self-adaptive technologies at all levels of the computing framework. He also worked in both industrial and CATRENE projects in the field of control infrastructures for multi/many-core architectures. From 2013 to 2016, he worked on the FP7 FiPS project as software WP leader, in Neuro-DSP (funded by a French national FUI grant) and actively participated to multiple H2020 project setups including M2DC and Exanode. He is currently working in industrial projects on neuro- and embedded computing supporting SMEs and large enterprises. His research interests include self-adaptation techniques based on observation, control and actuators for high performance and low-power computations as well as neuro-inspired processing chains.

Dr. Karim Ben Chehida received his PhD degree in Signal Processing and Communications, from the University of Nice Sophia Antipolis, France, in 2004. He joined the IC Design & Embedded Software Division of CEA (French Atomic Energy Commission) in 2005 as a research engineer to work on system level resource and power management for embedded parallel architectures.
His main research interests include smart sensors design and self-aware and autonomous system control.

Dr Henri-Pierre Charles is research director at CEA-LIST since September 2010. He was previously assistant professor in Versailles University during 17 years. He has supervised many PhD theses on code optimizations and High performance computing. His research interests are in dynamic compilation, Low level code optimization and new methods for code generation for high performances and multimedia applications. He has developed the concept of "compilettes" that can be defined as tiny code generators embedded into applications, able to generate optimal code depending on the data characteristics. This notion is used in heterogeneous architecture context, where code should be generated for CPU and/or accelerators and/or special devices such as in memory computing architecture.

Mr. Christian Fabre received his engineering degree from ENSIMAG (Grenoble, France) in 1990 while working on a Transputer routing kernel. He joined the OPEN SOFTWARE FOUNDATION Research Institute in 1993 to work languages, Java Virtual Machines, compilation and embedded software components. He contributed to a MDA/MDE approach for top-down design of hardware/software systems from the early 2000s to 2016, and is now working on variable precision. He joined CEA in 2009. He was involved in various collaborative projects and coordinated of PRO3D, a FP7 project on multicore, and of COPCAMS, an Artemis/ECSEL project of more than 20 partners.

Per Stenström is a professor of computer engineering at Chalmers University of Technology since 1995. His research interests are on design principles for high-performance computer systems with an emphasis on high-performance memory systems. He has authored or co-authored three textbooks and more than a hundred publications in international journals and conferences. He is regularly serving program committees and acting as editor for major conferences and journals in the computer architecture field: ISCA, HPCA, IEEE Trans. on Parallel and Distributed Processing Systems, Journal of Parallel and Distributed Computing and he is the founding Editor-in-Chief of Transactions on High-Performance Embedded Architectures and Compilers. He co-founded the HiPEAC Network of Excellence. He has acted as general and program chair for a large number of conferences including the ACM/IEEE Int. Symposium on Computer Architecture, the IEEE High-Performance Computer Architecture Symposium, and the IEEE Int. Parallel and Distributed Processing Symposium. He is a Fellow of the ACM and the IEEE and a member of Academia Europaea and the Royal Swedish Academy of Engineering Sciences.

Ioannis Sourdis is an Associate Professor in Computer Engineering at Chalmers University of Technology, Sweden. He has an engineering diploma Dipl-Eng ('02) and a MSc ('04) in electronic and computer engineering from the TU Crete, Greece, and a PhD ('07) in computer engineering from TU Delft, The Netherlands. His research interests include architecture and design of computer and networking systems, reconfigurable computing, interconnection networks and multiprocessor parallel systems, fault-tolerant computing and energy-aware computing. From 2007 until 2010, Sourdis participated in the coordination of the HiPEAC NoE cluster on Reconfigurable Computing. He has co-authored about 50 papers in Int. conferences and journals, cited in over 1000 papers. He is participating in the technical committees of 14 Int. conferences; he is reviewer in 21 Int. journals and more than 30 Int. conferences. Sourdis holds a patent in an address lookup technique for network routing. He participated in the Pro3, EASY, SARC and HiPEAC European projects, coordinated the DeSyRe FP7 project, and currently participates in EMC2, SHARCS, COSSIM, and ECOSCALE H2020 projects. He is also member of the HiPEAC NoE, member of the management committee of the MEDIAN Cost Action, member of IEEE and ACM.

Miquel Pericàs received his MS and Ph.D. from the Polytechnic University of Catalonia (UPC) in 2002 and 2008, respectively. His Ph.D. thesis focused on the design of out-of-order processors capable of handling thousands of in-flight instructions, so-called KILO-Instruction Processors.

In 2008 he joined BSC as a senior researcher, where he worked on reconfigurable supercomputing and parallel computing. In 2012 he joined the Tokyo Institute of Technology as a postdoctoral fellow, where he developed performance tools for the analysis of parallel software, with a focus on the memory hierarchy. In 2014 he joined Chalmers University of Technology as a postdoc to work in the ERC MECCA and SSF Scheme projects. From 2014 to 2016 he was also the assistant editor of the HiPEAC Newsletter.

Since 2016 he is an assistant professor at the computer engineering division of Chalmers University of Technology. His research interests include parallel computer architectures, runtime systems, and high-performance computing.

Pedro Trancoso is a Senior Lecturer at the Computer Engineering Division, Computer Science and Engineering Department, Chalmers University of Technology. Previously he was an Associate Professor at the Department of Computer Science at the University of Cyprus. He has a PhD and MSc. in Computer Science from the University of Illinois at Urbana-Champaign, USA. His research interests are in the area of Computer Architecture and include Multi-core Architectures, Memory Hierarchy, Parallel Processing and Programming Models, Database Workloads, High-Performance Computing, Approximate Computing, and Reversible Computing. The latest funding for his research include the participation in the UniServer EU H2020 project (3 years, starting 2/2016), Reversible Computation EU COST (4 years, started 4/2015), TERAFLUX EU FP7 IP project (4 years, completed in 2014) and the lending of a 48-core experimental processor, the Intel SCC, by the Intel Corporation. He is also a member of the HiPEAC Network of Excellence.

Dr. Carlo Cavazzoni graduated in Physics at the University of Modena in 1994 and got a PhD in computational condensed matter physics at the International School for Advanced Studies (ISAS-SISSA) of Trieste in 1998. He is presently a staff member of the CinecaHPC Department. He collaborates with different user communities to enable applications on massively parallel systems and innovative architecture solutions. He is responsible for the parallel design of QUANTUM ESPRESSO suite of codes. He is author and coauthor of several papers published in prestigious international reviews including Science, Physical Review Letters, Nature Materials, and many others.

Dr. Giuseppe Fiameni leads the "HPC Services" group of the Cineca High Performance Computing Department, the largest HPC centre in Italy. Over the course of his career, he has been involved in many R&D projects about computing and data architecture, data intensive applications, and data management systems. He is one of the architects of the Fenix Research Infrastructure (www.fenix.ri.eu) providing services and resources to the Human Brain Project.

Fabrizio Magugliani (MS in Aerospace Engineering at Politecnico di Milano, PhD in Energetics at Politecnico di Milano) is currently Strategic Planning and Business Development Director at E4 Computer Engineering SpA. During his 30-year long career, Ing. Magugliani has always been involved in HPC projects working in different roles with companies like SGI, Linux Networx and SiCortex. Most notably, Ing. Magugliani has developed solutions for the scientific and engineering communities leveraging the synergies among HPC, advanced visualization, storage and applications. In addition to his background in HPC, Ing. Magugliani has spent 6 years working in a leader engineering company, developing fluid–structure interaction models and authoring technical papers, with the objective to understanding the problems faced by engineering companies and develop the methodology for better serving these customers via products and solutions tailored for their needs. Ing. Magugliani has a specific interest in Computational Fluid Dynamics and its applications on HPC systems, including advanced visualization techniques, load balancing techniques, parallel optimization of solvers.

Cosimo has been working in IT for thirty years, playing the role of CTO in many important companies. In 2002 he founded E4 Computer Engineering, together with other partners, becoming CTO and Member of the Board of Directors. As a technology enthusiast, Cosimo actively scouts and tests new technologies, traveling to the world. With his experience on hardware, he was able to take the company to a very high level in the world of high performance computing, creating a R&D division that can now tackle the most challenging requests and offer complete solutions in the market of HPC, Big Data, Analytics, Artificial Intelligence.

Babak is a Professor in the School of Computer and Communication Sciences and the founding director of the EcoCloud research center at EPFL. He has made numerous contributions to computer system design and evaluation including multiprocessor architecture for the WildCat/WildFire severs by Sun Microsystems (now Oracle), memory prefetching technologies in IBM BlueGene and ARM cores, and server evaluation methodologies used by AMD, HPE and Google PerfKit. His recent work on workload-optimized server processors lays the foundation for Cavium ThunderX. He is a recipient of a number of distinctions including a Sloan Research Fellowship. He is a fellow of ACM and IEEE.

Johan Eker is a Principal Researcher at Ericsson, Sweden. He received his Ph.D. in automatic control from Lund University in 1999. After a brief stint in industry he joined the Ptolemy group at UC Berkeley in the US in 2001 working on the the CAL Actor Language, which later was turned into a global ISO standard by the MPEG organisation. He has been with Ericsson Research since 2003 working on embedded software for mobile phones, including operating systems, programming languages, compilers, and distributed systems. During the period 2008-2011 he acted as the coordinator of the European FP-7 research project ACTORS. Since February 2013 he is also adjoint associate professor at Lund University.

Pirmin Vogel received his B.Sc., M.Sc. and Ph.D. de¬grees in elec¬tri¬cal en¬gi¬neer¬ing and in¬for¬ma¬tion tech¬nol¬ogy from the Swiss Fed¬eral In¬sti¬tute of Tech¬nol¬ogy Zurich (ETH Zurich), Switzer¬land. He is currently holding a position as postdoctoral researcher in the Digital Circuits and Systems Group led by Prof. Dr. Luca Benini at the Integrated Systems Laboratory of ETH Zurich. His re¬search in¬ter¬ests in¬clude dig¬i¬tal sig¬nal pro¬cess¬ing and em¬bed¬ded het¬ero¬ge¬neous sys¬tems-on-chip with a fo¬cus on op¬er¬at¬ing sys¬tem, dri¬ver, run¬time and pro¬gram¬ming model sup¬port for ef¬fi¬cient and trans¬par¬ent ac¬cel¬er¬a¬tor pro¬gram¬ming.

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the William D. and Nancy W. Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, and bioinformatics. He is especially interested in interactions across domains and between applications, system software, compilers, and microarchitecture, with a major current focus on memory and storage systems. A variety of techniques he, together with his group and collaborators, have invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. His industrial experience spans starting the Computer Architecture Group at Microsoft Research (2006-2009), and various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google.

He received the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, faculty partnership awards from various companies, a healthy number of best paper or "Top Pick" paper recognitions at various computer systems and architecture venues, and the ACM Fellow recognition "for contributions to computer architecture research, especially in memory systems."

His computer architecture course lectures and materials are freely available on YouTube, and his research group makes software artifacts freely available online.

Frank K. G端rkaynak, obtained his B.Sc. and M.Sc. degrees from the Istanbul Technical University, and his Ph.D. degree from the Integrated Systems Laboratory of ETH Zurich. Since 2008 he is with the Microelectronics Design Center of ETH Zurich, involved in research and teaching on the design and test of digital integrated circuits (see chip gallery) and is a member of the PULP project.

Luca Benini holds the chair of digital Circuits and systems at ETHZ and he is Professor at the University of Bologna. He is also currently serving as Chief Architect for P2012/STHORM project in STmicroelectronics, Grenoble. He received a Ph.D. degree in electrical engineering from Stanford University in 1997.

Dr. Benini's research interests are in energy-efficient system design and Multi-Core SoC design. He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications.

He has published more than 600 papers in peer-reviewed international journals and conferences, four books and several book chapters. He is a Fellow of the IEEE and a member of the Academia Europaea and has served for two terms as a member of the steering board of the ARTEMISIA European Association on Advanced Research & Technology for Embedded Intelligence and Systems.

Professor Manolis Katevenis received his PhD degree in Computer Science from U.C. Berkeley in 1983, where he was the chief implementer of the RISC II single-chip microprocessor (precursor of the SUN SPARC architecture); for this work he received the 1984 ACM Doctoral Dissertation Award. In 1984-85 he was Assistant Professor at Stanford University, and since 1986 he is with the Univ. of Crete, where he is currently Professor, and with FORTH-ICS where he heads the CARV Laboratory; see http://users.ics.forth.gr/~kateveni. He co-founded the HiPEAC Network of Excellence.

Dionisios N. Pnevmatikatos is a Professor and Director of the Microprocessor and Hardware Laboratory (MHL) at the School of Electrical and Computer Engineering, Technical University of Crete (TUC), and a research associate with FORTH-ICS since 1997. He received his PhD in Computer Science in 1995 from the University of Wisconsin–Madison. He has participated as a coordinator in FASTER FP7 EU project, and as Principal Investigator in the DeSyRe FP7 and the AXIOM, dRedBox (ongoing), and EXTRA (ongoing) H2020 projects, as well as for several national projects. His research interests include Computer Architecture, with a focus on using reconfigurable computing to create highly efficient, accelerated, heterogeneous parallel/rack-scale systems. He has also worked on Reliable System Design, Networking Hardware and Network Processors, Application Acceleration, Custom and Application-Specific Architectures, and Hardware Acceleration of Bioinformatics Algorithms. He has been in the Program Committee of conferences such as ISCA, FPL and DATE in Computer Architecture and Reconfigurable System topics, and has been a Program (co)chair for SAMOS 2018 and FPL 2011.

Angelos Bilas is currently a Professor of Computer Science at the University of Crete, Greece, where he has also held an Associate Professor position between 2002-2011, and a collaborating researcher at FORTH-ICS. Prof. Bilas received his diploma in Computer Engineering from the University of Patras in 1993, and the Masters and Ph.D. degrees in Computer Science from Princeton University, NJ in 1995 and 1998 respectively. Between 1998-2002 he held an Assistant Professor position with the ECE Department at the University of Toronto. His current interests include systems software for efficient storage systems, computing and storage architectures, low-latency high-bandwidth communication protocols, and runtime-system support for parallel systems. His work has been published in prestigious conferences in computer architecture and systems. He has been the PI for more than 35 EU or nationally funded projects and has been the coordinator of the FP7 EU project IOLanes [2010-2013]. He has collaborated extensively with international industry while his research has been licensed to startups (two rounds of research results) and has been used in products by Fortune50 companies. [http://www.ics.forth.gr/~bilas]

Polyvios Pratikakis is an Assistant Professor at the Computer Science Department of the University of Crete, and collaborating reseracher at ICS-FORTH. He graduated from the Department of Electrical and Computer Engineering of the National Technical University of Athens in 2002. He received a Master's degree in Computer Science in 2004 and a Ph.D. in 2008 from the University of Maryland. His research interests include programming languages, type systems, dynamic and static analysis, parallellism and concurrency, parallel and distributed runtime systems, memory management, and data analytics. He has successfully led or participated in several National and European research projects.

Senior Research Engineer at FORTH, working on the design, prototyping, and evaluation of experimental computing systems, in particular architectures and efficient systems software for datacenter servers and storage systems. Dr. Marazakis received his Ph.D. degree in Computer Science from the University of Crete, Greece in 2000.

Christos Kozanitis is a research collaborator at FORTH-ICS. He received his M.S. and Ph.D in Computer Science and Engineering from the University of California, San Diego in 2009 and 2013 respectively. Parts of his phd work influenced products from companies such as Cisco and Illumina. He also held a two-year postdoctoral appointment at the AMP Lab of the University of California, Berkeley, where he used and adapted state of the art big data technologies, such as Apache Spark SQL, Apache Parquet and Apache Avro to process large amounts of DNA sequencing data. His current research interests involve the improvement in software, storage and hardware level of modern datacenters in order to speed up the processing of big data analytics workloads.

Koen De Bosschere is professor of Computing Systems at Ghent University in Belgium, and leader of the Computer Systems Lab. He is the editor-in-chief of ACM Transactions on Architecture and Code Optimization (TACO) and coordinator of HiPEAC - the premier network of computing systems researchers in Europe. He is co-editor of the bi-annual HiPEAC vision document and organizer of the yearly ACACES summer school. At Ghent University, he is the Head of the Electronics and Information Systems Department and he manages the university-wide student-entrepreneurship project for which he received the Hermes Award in 2012. He co-authored 100 publications over the last 10 years. His research interests include computer architecture, system software, code optimization, and software security. He earned B.S. and Ph.D. degrees in Electronics Engineering and Computer Science at Ghent University.

Bjorn De Sutter is a Professor in the Computer Systems Lab in the Electronics and Information Systems Department of Ghent University. His areas of interest include Coarse-grained reconfigurable computing: compilation techniques and design space exploration, Whole-Program Optimization & Compiler Optimization: Performance and Code Size, and Compiler Techniques for Software Protection: software diversity, obfuscation, side-channel mitigation, code hardening. His research at Ghent University has been funded by the Fund for Scientific Research - Flanders (FWO), the European Commission, the the Agency for Innovation by Science and Technology (IWT), and several bilateral industrial collaborations.

Since November 2013, Bjorn coordinates the European research project ASPIRE, which performs research into Advanced Software Protection: Integration, Research, and Exploitation. In the above areas, Bjorn published over 50 papers in international journals and conferences. He also participated in more than 20 program committees in these research areas. For his Master thesis (in collaboration with Mark Christiaens) on multimedia architectures, he won the yearly Barco Award for Graduation Dissertations 1998, awarded by the Fund for Scientific Research - Flanders.

In 2013, Bjorn won a HiPEAC Technology Transfer Award. From November 2002 to July 2003, he visited IBM T.J. Watson Research Center to collaborate with Frank Tip on whole-program optimization of Java programs by means of automated container class optimization and refactoring. This work (and the work building on it) was recognized as a "Research Accomplishment" at IBM Research (in the category "Fundamental Contributions to Science and Technology"). From 2005 to 2007, Bjorn worked in the compiler and computer architecture team at IMEC. From late 2006 on, he lead the team that developed the ADRES coarse-grain dynamically reconfigurable array architecture and the corresponding ANSI-C compiler. From 2008-2011, he was also a faculty member of the Embedded Systems Group of the Department of Electronics and Informatics at the Vrije Universiteit Brussel.

I am a Professor (hoogleraar BOF-ZAP) at Ghent University, Belgium, in the Department of Electronics and Information Systems (ELIS). I obtained my MS and PhD degrees from Ghent University in 1998 and 2002, respectively. My research interests include computer architecture and the hardware/software interface in general, and performance analysis, evaluation and modeling more in particular.

Prof. Dr.-Ing. Michael M. Resch is the director of the High Performance Computing Center Stuttgart (HLRS) and the director of the Department for High Performance Computing at the University of Stuttgart / Germany. Furthermore, he is a chairman of the board of the German Gauss Center for Supercomputing (GCS), and is a member of the advisory councils for the Triangle Venture Capital Group, the IDC HPC User Forum and a number of various other foundations. He has over 25 years of experience in High Performance Computing and contributed his proven knowledge and experience to a variety of conferences and community activities in the domain of supercomputing over the last decades. Michael Resch holds a degree in Technical Mathematics from the Technical University of Graz / Austria and a PhD in Engineering from the University of Stuttgart / Germany. In 2002 he held an Assistant Professorship at the department of computer science of the University of Houston / Texas. In 2009, he was awarded an honourable doctoral degree from the National Technical University of Donezk / Ukraine. In 2011, Michael Resch was awarded an honourable doctoral degree from the Russian Academy of Science. In 2014, he was awarded an Honorary Professorship of the Russian Academy of Sciences.

Dr.-Ing. Bastian Koller joined the High Performance Computing Center Stuttgart (HLRS) in 2004 after his diploma degree in computer science and received his PhD in 2011. Starting as a research assistant in the area of Grid Computing, Cloud Computing and High Performance Computing, he led from 2007 to 2013 an own research group on “Service Management and Business Processes”. Dr. Koller was Technical Manager of one of the first Cloud related IST FP6 projects: BREIN. Since 2013 he is responsible for the research strategy of HLRS and is since 2014 acting as Managing Director of the centre. Since he started at HLRS, he was and still is involved in many research activities, national and international, in HPC and synergetic topics such as Cloud or Data Analytics. He worked in projects such as HPC Europa, DEISA, DORII, IRMOS, CRESTA, BREIN, BeinGRID, BonFIRE, Fortissimo and is coordinator of the EXCELLERAT Centre of Excellence on HPC engineering applications.

Dr. Andrea Reale is a member of the High Performance Systems team in IBM Research, Ireland. His professional interests center around large scale, parallel and distributed data processing systems. His research activities focus on novel software stacks for data-intensive workloads that include specialized accelerators, ad-hoc operating system/kernel enhancements, and distributed middleware running on both bare-metal or virtual infrastructures. Dr. Reale holds a Ph.D. in Computer Engineering (Distributed Systems) from the University of Bologna. He received cum-laude M.Sc. and B.Sc. diplomas in Computer Engineering from the same University in 2010 and 2008, respectively.

Dr Christian Pinto is a Research Scientist in the High Performance Systems group at IBM Research - Ireland. His research activities are focused on novel cloud computing paradigms, and applications of distributed systems and cloud computing concepts to the field of Artificial Intelligence. In the past he has been involved in research on virtualization, mostly applied to KVM, and parallel programming applied to multi- and many-core computing systems. He holds a Ph.D. in Computers and Electronic Engineering from University of Bologna, received in 2015. Dr. Pinto holds a M.Sc. from the same university (2010) and a B.Sc. from University of Catania (2017), both in Computers Engineering.

Dr Michael Johnston is a senior research engineer and manager of the High Performance Systems group at IBM Research - Ireland, and technical lead of IBM Chemistry group at the IBM/STFC Hartree Centre. His research interests span the physical and computer science domains but share the common theme of making HPC methods central to industry. Particular research topics include in-silco molecular design and discovery, and construction and orchestration of large-scale HPC workflows. In the past he has been involved in research on bimolecular dynamics and energetics, and performance characterisation and optimisation on IBM BlueGene and Power supercomputing platforms. While with IBM he has worked with a variety of partners including STFC, Unilever, the SKA and the Oasis LMF. He holds a Ph.D. in Biophysics from University of Pompeu Fabra, Barcelona (2009), an M.Sc. in High Performance Computing from Trinity College Dublin (2003), and a B.Sc.in Experimental Physics (2001) from the same university

Cristiano Malossi received his B.Sc. in Aerospace Engineering and his M.Sc. in Aeronautical Engineering from the Politecnico di Milano (Italy) in 2004 and 2007, respectively. After working one year on computational geology problems in collaboration with ENI, he moved to Switzerland where in 2012 he got his Ph.D. in Applied Mathematics from the Swiss Federal Institute of Technology in Lausanne (EPFL), with a thesis focused on the development of algorithms and mathematical methods for the numerical simulation of cardiovascular problems. After winning the IBM Research Prize for his PhD thesis, in July 2013 Cristiano joined IBM Research - Zurich in the Foundations of Cognitive Solutions group. Cristiano is a recipient of the 2015 ACM Gordon Bell Prize and 2016 IPDPS Best Paper Award.

His main research interests include: High Performance Computing, Energy-Aware Algorithms and Architectures, Deep Neural Networks, Graph Analytics, Numerical Analysis, Computational Fluid Dynamics, Aircraft Design, Computational Geology, and Cardiovascular Simulations.

Costas Bekas is managing the Foundations of Cognitive Computing group at IBM Research-Zurich. He received B. Eng., Msc and PhD diplomas, all from the Computer Engineering & Informatics Department, University of Patras, Greece, in 1998, 2001 and 2003 respectively. Between 2003-2005, he worked as a postdoctoral associate with prof. Yousef Saad at the Computer Science & Engineering Department, University of Minnesota, USA. He has been with IBM since September 2005. Costas's main research interests span HPC, massive scale analytics and cognitive computing, energy aware algorithms and architectures. Costas is a recipient of the PRACE 2012 award and the ACM Gordon Bell 2013 prize.

Christoph Hagleitner leads the "Heterogeneous Cognitive Computing Systems" group at the IBM Research – Zurich Lab (ZRL) in Ruschlikon, Switzerland. The group focuses on heterogeneous computing systems for cloud datacenters and HPC. Applications include big-data analytics and cognitive computing. He obtained a diploma degree in Electrical Engineering from ETH, Zurich, Switzerland in 1997 and and a Ph.D. degree for a thesis on CMOS-integrated Microsensors from ETH, Zurich, Switzerland in 2002. In 2003 he joined IBM Research to work on the system architecture of a novel probe-storage device (“millipede”-project). In 2008, he started to build up a new research group in the area of accelerator technologies. The team initially focused on on-chip accelerator cores and gradually expanded its research to heterogeneous systems and their applications.

Paul H J Kelly graduated in Computer Science from University College London in 1983, and moved to Westfield College, University of London, for his PhD. He came to Imperial College, London, in 1986, working on fault-tolerant wafer-scale multicore architectures, and parallel functional programming. He was appointed as Lecturer in 1989, and Professor of Software Technology in 2009. He leads Imperial's Software Performance Optimisation research group, and he is also co-Director of Imperial's Centre for Computational Methods in Science and Engineering. He has worked on single-address-space operating systems, scalable cache coherency protocols, bounds checking, pointer analysis, graph algorithms, performance profiling, and custom floating-point arithmetic. His major current projects include Firedrake, PyOP2 and SLAMBench. The broad theme of his current research is domain-specific optimisations.

Spencer Sherwin is Head of Aerodynamics and Professor of Computational Fluid Mechanics in the Department of Aeronautics and Director of Research Computing Service at Imperial College London. He received his MSE and PhD from the Department of Mechanical and Aerospace Engineering Department at Princeton University. Prior to this he received his BEng from the Department of Aeronautics at Imperial College London.

Albert is a research scientist at Google. He has been a research scientist at Inria from 2000 to 2018. He graduated from École Normale Supérieure de Lyon and received his PhD from the University of Versailles in 1999 (awarded two national prizes). He has been a visiting scholar at the University of Illinois, an invited professor at Philips Research, and a visiting scientist at Facebook Artificial Intelligence Research. Albert Cohen works on parallelizing and optimizing compilers, parallel programming languages and systems and synchronous programming for reactive control systems. He served as the general or program chair of major conferences, including PLDI, PPoPP, HiPEAC, CC, the embedded software track of DAC, and as a member of the editorial board of ACM TACO and IJPP. He coauthored more than 180 peer-reviewed papers and has been the advisor for 26 PhD theses. Several research projects initiated by Albert Cohen resulted in effective transfer to production compilers and programming environments in industry.

Erven Rohou obtained his PhD from the University of Rennes 1 in 1998. He was a post-doc at Harvard University in 1999. He spent 9 years working in R&D at STMicroelectronics before joining Inria in 2008. He is now a senior researcher and the head of the Inria PACAP project-team. His research interests include static compilation, JIT compilation, and dynamic binary optimization.

Fabrice Rastello received his PhD degree in computer science from ENS Lyon in 2000. He then worked as an engineer for STMicroelectronics for two years before becoming a full-time researcher at Inria, Grenoble, France. He is now the team leader of the Inria Compiler Optimization and Runtime SystEms (CORSE) Group.

His past research was on Compiler optimizations for DSP/VLIW/Media like embedded processors, and focused on SSA-based optimizations. He is editor and author of the "SSA-based Compiler Design" book. He is also an expert on loop transformations such as tiling (PhD thesis). His recent research activities include: 1. hybrid analyses (both static and dynamic), and hybrid compilation for loop transformations at machine level; 2. automatic tools for analysis of I/O complexity of programs with applications to algorithm analysis, compiler assessment and algorithm-architecture co-design; 3. software memory management for distributed memory systems.

Philippe Clauss received his PhD degree in computer science from the University of Franche-Comté, France, in 1990, and his "Habilitation" from the University of Strasbourg, France, in 2000. He worked as Assistant Professor until 2002 and then Professor at the University of Strasbourg. He is now the team leader of the Inria Compilers for Multicore Architectures (CAMUS) Group.

His research activities include: 1. Mathematical tools for precise analysis and tranformation of loops (Polyhedral Model, Ehrhart Polynomials); 2. Runtime speculative loop parallelization (APOLLO framework); 3. Language extensions for explicit code optimization (XFOR loop structure).

Emmanuel Jeannot is a Senior Research Scientist at Inria. He is doing his research at INRIA Bordeaux Sud-Ouest and at the LaBRI laboratory since 2009. From 2005 to 2006 he was researcher at INRIA Nancy Grand-Est. In 2006 I was a visiting researcher at the University of Tennessee, ICL laboratory. From 2000 to 2005 he was assistant professor at the Université Henry Poincaré. During the period from 2000 to 2009 he did his research at the LORIA laboratory. He got his PhD and Master degree of computer science (resp. in 1996 and 1999) both from Ecole Normale Supérieur de Lyon, at the LIP laboratory. His main research interests lies in parallel and high-performance computing and more precisely: process placement, topology-aware algorithms, scheduling for heterogeneous environments, data redistribution, algorithms and models for parallel machines, distributed computing software, adaptive online compression, and programming models.

Vít Vondrák is the managing director at IT4Innovations National supercomputing center and associated professor at VŠB - Technical University of Ostrava. His expertise is in numerical linear algebra, optimization methods, high performance computing. He is the member of the PRACE Council (Partnership for Advanced Computing in Europe) representing the Czech Republic. He is/was co-investigator of 4 FP7 projects PRACE-1IP, PRACE-2IP, PRACE-3IP, HARPA and H2020 project PRACE-4IP. Leader of mathematical modelling group in the project FLOREON+ (http://floreon.eu) - system for disaster management support. Principal investigator of the project Intel Parallel Computing Center and project of the Large infrastructures of the Czech Republic. Vít Vondrák is author of more than 60 scientific papers, 7 papers in journals with impact factor, h-index 4 on WoS.

Tomas Kozubek is the Scientific Director and professor of applied mathematics at the Czech National Supercomputing Centre IT4Innovations at VŠB-Technical University of Ostrava. He is specialized on development of scalable algorithms for massively parallel solution of engineering problems, domain decomposition techniques, and optimization methods. He is author or co-author of more than 60 articles published in conference proceedings and journals. He was PI for the Czech Republic of the project FP7-ICT EXA2CT (Exascale Algorithms and Advanced Computational Techniques). Currently, he is PI for the Czech Republic of the H2020-MSCA-ITN EXPERTISE project (models, EXperiments and high PERformance computing for Turbine mechanical Integrity and Structural dynamics in Europe) and co-coordinator of Intel Parallel Computing Center at IT4Innovations and Digital Innovation Hub at IT4Innovations in HPC and HPDA recognized and registered by European Committee.

Lubomír Říha is head of the Infrastructure Research Lab at IT4Innovations National Supercomputing Centre (IT4I). Previously he was a senior researcher in the Parallel Algorithms Research Lab at IT4I and a research scientist in High Performance Computing Lab at The George Washington University, ECE Department. He has received his Ph.D. and M.Sc. degrees in Electrical Engineering from Czech Technical University in Prague, Czech Republic in 2011 and D.Sc. degree in Computer Science from Bowie State University, USA. He was investigator of FP7 EXA2CT project and Intel Parallel Computing Center and principal investigator of the H2020 READEX project at IT4I. He is also a co-principal developer of the ESPRESO library. His research interests are high performance computing, energy efficient computing, acceleration of scientific and engineering applications using multi- and many-core accelerators, development of scalable linear solvers, signal and image processing.

Jan Martinovič is currently Head of Advanced Data Analysis and Simulations Lab at IT4Innovations. His research activities are focused on information retrieval, data processing, design and development of information systems and disaster management. His activities also cover a development of HPC as a Service Middleware which allows to use HPC infrastructure remotely by specific API. He had previous experience with coordination of the different contracted research activities with international and national companies such as Microsoft Corporation USA or ArcelorMittal Frýdek-Místek a.s. Czech Republic and had responsibility for the technical coordination of the several national projects. He is currently the leader of IT4I as a partner of the two H2020-FETHPC-2014 projects ANTAREX (AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems) and ExCAPE (Exascale Compound Activity Prediction). He is also responsible for the research and development team of FLOREON+ system (http://floreon.eu) - a system for disaster management support. He has published more than 100 papers in international conferences and journals.

Prof. Dr.-Ing. André Brinkmann is a full professor at the computer science department of JGU and head of the ZDV (since 2011). He received his Ph.D. in electrical engineering in 2004 from the University of Paderborn and has been an assistant professor in the computer science department of the University of Paderborn from 2008 to 2011. Furthermore, he has been the managing director of the Paderborn Centre for Parallel Computing PC2 during this time frame. His research interests focus on the application of algorithm engineering techniques in the area of data centre management, cloud computing, and storage systems. He has published more than 100 papers in renowned conferences and journals and is an associated editor of the ACM Transactions on Storage as well as a steering committee member of the IEEE Symposium on Massive Storage Systems and Technologies (MSST) and IEEE International Conference on Networking, Architecture, and Storage (NAS). Prof. Brinkmann is a member of the steering committee of the French Grid'5000.

Dr. Manuel Baumgartner is a post-doc at the Data Center of the Johannes Gutenberg University of Mainz. He received his Ph.D. in 2016 from the Johannes Gutenberg University of Mainz.

Nectarios Koziris is a Professor of Computer Science and the Dean of the School of Electrical and Computer Engineering at the National Technical University of Athens. His research interests include parallel and distributed systems, interaction between compilers, OS and architectures, datacenter hyperconvergence, scalable data management and large scale storage systems. He has co-authored more than 140 research papers with more than 2800 citations (h-index:24). From 1998 he has been involved in the organization of many international scientific conferences including IPDPS, ICPP, SC, SPAA, etc. He has given many invited talks in conferences and universities. He is a recipient of two best paper awards for his research in parallel and distributed computing (IEEE/ACM IPDPS 2001 and CCGRID 2013) and had received honorary recognition from Intel (2015) for his research and insightful contributions in transactional memory (TSX synchronization extensions). He has participated as a partner or consortium coordinator in several EU projects involving large-scale systems (GREDIA, GRID4ALL, ARCOMEM, CELAR, ASAP, EGI, PRACE etc). He is a member of the IEEE Computer Society, senior member of the ACM, elected chair of the IEEE Greece Section and started the IEEE Computer Society Greece. To promote the open source software in Greece, he co-founded the Greek Free/Open Source Software Society (GFOSS-www.ellak.gr) in 2008, with members 29 Greek Universities and Research Centers, where he is now serving as the Vice-Chair of the Board of Directors. He was a member of the European Commission's cloud computing expert group (2012-2013) which was established with the aim to develop a cloud computing vision for Europe and future research directions and he is also serving in the EC task force for the Next Generation Internet. For the last 10 years (2004-2014), Nectarios has served as the Vice-Chair for the Greek Research and Technology Network-GRNET. He was the founder of the ~okeanos project, a public Cloud IaaS infrastructure, among the biggest ones in the European public sector (topping out beyond 10.000 active VMs), powered by the open source Synnefo software (www.synnefo.org). ~Okeanos and ~okeanos-global for the GÉANT community, offer IaaS services to thousands of academics and researchers around Europe. He has also served (2013-2014) as a member of the BoD for the Athena Research and Innovation Center in Information, Communication and Knowledge Technologies. He is an advisor to Arrikto Inc., a fresh startup based in Palo Alto, California, that develops storage intelligence to access, manage, and store data in large-scale, heterogeneous and hybrid environments. For more: http://www.cslab.ece.ntua.gr/~nkoziris

Dimitrios Soudris received his Diploma and Ph.D. in Electrical Engineering from the University of Patras, Greece, in 1987 and 1992, respectively. He was working as a Professor in Dept. of Electrical and Computer Engineering, Democritus University of Thrace for thirteen years since 1995. He is currently working as Associate Professor in School of Electrical and Computer Engineering, Dept. Computer Science of National Technical University of Athens, Greece.

His research interests include embedded systems design, reconfigurable architectures, reliability and low power VLSI design. He has published more than 400 papers in international journals and conferences. Also, he is coauthor/coeditor in seven books of Kluwer and Springer. He is leader and principal investigator in numerous research projects funded from the Greek and German Government and Industry, European Commission (ESPRIT II-III-IV and 5th & 7th IST, Horizon 2020), ENIAC-JU and European Space Agency. He has served as General Chair and Program Chair for PATMOS 99 and 2000, respectively, General Chair of IFIP-VLSI-SOC 2008 and General Co-Chair of PARMA Workshop 2013. Also, he received an award from INTEL and IBM for the EU project LPGD 25256, awards in ASP-DAC 05 and VLSI 05 for EU AMDREL project IST-2001-34379.

Dr. Georgios Goumas is a lecturer at the School of ECE of the National Technical University of Athens. He graduated from the Dept. of Electrical and Computer Engineering of the National Technical University of Athens (NTUA) (1999). He received a PhD Degree from the School of Electrical and Computer Engineering of NTUA in January 2004. His research interests include high-performance computing and architectures, cloud computing, resource allocation policies, resource-demanding applications, sparse algebra, automatic parallelizing compilers, parallel programming models, and concurrency control strategies. He has published more than 40 research papers in journals, international conferences and peer-reviewed workshop. He has worked in several European and National R&D programs in the field of High Performance Computing, Cloud Computing, Networking and Storage for IT systems (HellasHPC, SMART-PIV, PRACE, PRESEMT, DOLFIN). He is a member of the IEEE, HiPEAC and of the Technical Chamber of Greece.

Konstantinos Nikas received his Diploma in Electrical " Computer Engineering from the National Technical University of Athens and his Ph.D. in Computer Science from the University of Manchester. He is currently a senior researcher at the Computing Systems Laboratory (CSLab) of the School of Electrical and Computer Engineering of NTUA. His research interests include computer architectures, memory hierarchies, resource-aware scheduling, high performance computing and parallel programming models.

Cristina Silvano is an Associate Professor (with tenure) of Computer Engineering at Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria. She has recently been named IEEE Fellow (effective from 2017) by the IEEE Boards of Directors “for contributions to energy-efficient computer architectures”. She annually teaches basic and advanced courses on Computer Architectures and Operating Systems. She is currently Project Coordinator of the H2020-FET-HPC Europen Project ANTAREX (2015-2018) on "AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems”. Previously, she was Project Coordinator of two European projects: FP7-2PARMA (2010-2013) and FP7-MULTICUBE (2008-2010). Since 1996, she has started a continuous research collaboration with STMicroelectronics on power-aware embedded architectures. She was Principal Investigator of two industrial research projects funded by STMicroelectronics (2003-2008). She has been nominated Project Manager of the IBM/POLIMI Collaborative Innovation Center on Big Data Analytics (2015-Present).

She is an active contributor to the scientific community and she regularly serves as Member (or Track Chair) of the Program Committee of several top-level conferences such as DAC, ICCAD, DATE, NOCS, HPCA, MICRO, ASAP and FPL. Recently she was Program Chair of FPL 2015, the 25th International Conference on Field Programmable Logic and Applications. Previously, she was Program Co-Chair of ASAP2012, ARC2011, and SASP2010. She was General Co-Chair of SASP2009 and MICRO2008 (receiving the ACM Recognition of Service Award). From June 2015, she is Associate Editor of ACM Transactions on Architecture and Code optimization (TACO). She has served as Independent Expert Reviewer for the European Commission and for several science foundations such as the Agence National de la Recherche (F), the Swiss National Science Foundation (CH) and the Academy of Finland. She has been invited to give several talks/seminars and moderate panels all over the world.

Her current research focuses on Computer Architectures and Electronic Design Automation, with emphasis on power-aware design, design space exploration of embedded architectures, application autotuning for many-core architectures, Network-on-Chip architectures and technology-aware many-core architectures. She is co-author of more than 160 scientific publications on peer-reviewed international journals and conferences (including 17 IEEE/ACM Transactions and collecting one Best Paper Award). She is co-editor of 4 Special Issues and 3 scientific books. She is inventor/co-inventor of 11 international patents (7 out of 11 already granted). Based on Google Scholar, her h-index is 31 and her total number of citations is 3475.

She started her career as Design Engineer and then become Senior Design Engineer at the R&D Labs of Group Bull in Italy (1987-1996). Since 1992, she was part of the Bull-IBM Research team for the design of the first worldwide multiprocessor system based on PowerPC architecture. These multiprocessors have been commercialized as Bull Escala UNIX Servers and as IBM RS/6000 Multiprocessor Servers. she also spent several periods abroad as Visiting Engineer at Bull R&D Labs, Billerica (MA - USA), Visiting Engineer at VLSI Technology, in Munich (D) and in S. Jose (CA-USA) and Visiting Engineer at IBM Somerset Design Center, Austin (TX - USA).

Donatella Sciuto received her Laurea in Electronic Engineering from Politecnico di Milano and her PhD in Electrical and Computer Engineering from the University of Colorado, Boulder, and an MBA from Bocconi University. She is currently the Executive Vice Rector of the Politecnico di Milano and Full Professor in Computer Science and Engineering. She is in charge of both International relations for Engineering and Research Strategies. Her interests cover also ICT infrastructure and services, teaching innovation and MOOCs, diversity inclusion. Her main research interests cover the methodologies for the design of embedded systems and multicore systems, from the specification level down to the implementation of both the hardware and software components, including reconfigurable and adaptive systems. She has published over 300 scientific papers. She is a Fellow of IEEE and has served as President of the IEEE Council of Electronic Design Automation from 2011 to 2013. She is member of the IEEE Awards Committee and has been Chair of the IEEE Philips Award committee. She is member of the IEEE Fellow Committee. She has been Program Chair of DATE and DAC Conferences and General Chair of DATE and ESWEEK, and has covered organizational and scientific positions in the main IEEE Conferences in the area of EDA.

Marco Santambrogio is an Associate Professor at Politecnico di Milano since 2018, and an Adjunct Professor del College of Engineering of the University of Illinois at Chicago (UIC) since 2009. He was Research Affiliate with the Computer Science and Artificial Intelligence Laboratory (CSAIL) at Massachusetts Institute of Technology (MIT) from 2010 to 2015. He received his laurea (M.Sc. equivalent) degree in Computer Engineering from the Politecnico di Milano (2004), a M.Sc. degree in Computer Science from the University of Illinois at Chicago (UIC) in 2005 and his PhD degree in Computer Engineering from the Politecnico di Milano (2008). Prof. Santambrogio was a postdoc fellow at CSAIL, MIT.

He has been with the Micro Architectures Laboratory at the Politecnico di Milano, where he founded the Dynamic Reconfigurability in Embedded System Design (DRESD) project in 2004. In 2011, he founded the Novel, Emerging Computing System Technologies Laboratory (NECSTLab – http://necst.it/), merging together the two previously existing labs: MicroLab and VPLab, and he is, since then, in charge of the laboratory. He conducts research and teaches in the areas of reconfigurable computing, self-aware and autonomic systems, hardware/software co-design, embedded systems, and high performance processors and systems. Since 2001, he has been involved in several research projects in collaboration with industries such as Xilinx, Maxeler, ARM, Siemens Mobile and Nokia Siemens Network. With respect to Xilinx, Marco created and hosted the first two edition of the Xilinx PYNQ Hackathon, his research group has a strong and long history of collaborations with Xilinx Dublin, because of the work done on SDAccel and the roofline model, with Xilinx Colorado, because of the work done on the PYNQ platform and with Xilinx San José because of the Coursera courses and the Amazon AWS F1 research. In 2017 his group held a SDAccel, CAOS and Amazon F1 instances workshop at the IEEE ICCD Conference in Boston.

Marco D. Santambrogio is a senior member of both the IEEE and ACM, he is member of the IEEE Computer Society (CS) and the IEEE Circuits and Systems Society (CAS). He is or has been member of different program committees of electronic design automation conferences, among which: DAC, DATE, CODES+ISSS, FPL, RAW, EUC, IFIP VLSI Conference.

Research Interests

I am a member of the High Performance and Distributed Computing research cluster in the School of Electronics, Electrical Engineering and Computer Science at Queen's University Belfast. I have a long-held interest in the pragmatic use of formal specification notations to model and reason about systems, most recently parallel/distributed systems built using parallel patterns (algorithmic skeletons). Other interests include variability management, particularly in the context of software product lines and feature modelling. Previously I have worked in the areas of program transformation, formal methods, and language design for parallel systems.

I was chair of PDP 2013 and co-chair of PDP 2014 Recent Projects

cHiPSet (2015-2019) Cactos (2013-2016) ParaPhrase (2011-2015) CoreGRID (2004-2008)

A list of my publications can be found on ResearchGate (probably the most complete list). And on PURE.

I currently co-supervise five PhD students: Sakil Barbhuiya: Data collection and analytics. Esha Barlaskar: Scheduling jobs for cloud execution. Michael Campbell: Automated support for accelerator kernel development. Stuart McCool: Tool support for parallel application development. Stephen Murray: Feature Modelling for Parallel Systems.

Teaching

I teach two final-year courses: "Algorithms: Analysis and Applications" which explores the complexity of a range of classical algorithms including sorting, searching, pattern matching, etc. "High Performance Computing: Principles Of Parallel Programming" which explores fundamentals of parallel programming and emphasises practical aspects via MPI, OpenMP and CUDA. Previously I have taught courses on Introductory Programming, Concurrency Theory and Practice, Formal Methods (VDM), Computation Theory, Language Semantics, Human-Computer Interaction.

I am a member of the Data Science and Scalable Computing centre within the Queen's University Global Research Institute on Electronics, Electrical Engineering and Computer Science. My main interest is in the development of efficient software for heterogeneous systems, in particular using GPU accelerators. I also have interests in satisfiability solvers, satisfiability benchmarks, software product lines and feature modelling.

Current and Recent EU Projects

EcoScale, Rapid, NanoStreams, Handhold.

A list of my publications can be found on the QUB PURE site.

I currently co-supervise three PhD students. Konstantin Bakanov: Specifiation and efficient implementation of financial indicators; Esha Barlaskar: Scheduling jobs for cloud execution; Andrew McStea: Analytics for sports data.

Teaching

I teach a large first year discrete mathematics course "Reasoning for Problem Solving" and a third year course "Formal Methods" which uses VDM-SL. I have recently taught courses on High Performance and Distributed Computing and Algorithms.

Hans Vandierendonck is a Senior Lecturer (associate professor) in High-Performance and Distributed Computing in the school of Electronics, Electrical Engineering and Computer Science, at Queen's University Belfast He is a member of the Queen’s Institute for Electronics, Communications and Information Technology (ECIT). His research interests are in compilers, runtime systems and architectures for parallel systems with special attention to the programmability of such systems. Hans also has a vested interested in computer architecture, and particularly in cache architecture, prediction and performance evaluation. He has published over 100 peer-reviewed conference and journal contributions. He has served in programme committees for top conferences in his area (SC, ICS, IPDPS, ICPP, CCGrid), and regularly reviews for leading journals (ACM TACO, IEEE TC, IEEE TPDS, JPDC and Parallel Computing). He has fulfilled various roles in conference organisation: he is/was finance chair of IEEE CLUSTER 2018, programme co-chair of Track 9 at Euro-Par 2017, student travel grant chair at HPCA 2016, and publicity chair of HiPEAC 2009 and ISCA 2010. He was invited to lecture at the 2012 SICSA Summer School on Advances in Programming Languages at Heriot-Watt University and at the 2018 EPSRC-funded Manycore Summer School in Glasgow. His research has received competitive funding from the EU FP7 and H2020 programmes, the EC Maria Slodowska Curie Fellowship scheme, EPSRC and industry. Hans received the IBM Belgium Prize for Computer Science in 2000 for his graduation thesis and in 2004 for his PhD dissertation. His graduation thesis also received the Jozef Plateau prize from the Alumni Engineers Ghent in 2000. He is a Senior Member of IEEE, a Senior Member of ACM, a Fellow of the Higher Education Academy and a member of the EPSRC College of Peer Reviewers.

Rainer Leupers received the M.Sc. (Dipl.-Inform.) and Ph.D. (Dr. rer. nat.) degrees in Computer Science with honors from TU Dortmund in 1992 and 1997. From 1997-2001 he was the chief engineer at the Embedded Systems chair at TU Dortmund. In 2002, he joined RWTH Aachen University as a professor for Software for Systems on Silicon. His research comprises software development tools, processor architectures, and system-level electronic design automation, with focus on application-specific multicore systems. He published numerous books and technical papers and served in committees of the leading international EDA conferences. He received various scientific awards, including Best Paper Awards at DAC and twice at DATE, as well as several industrial awards. Dr. Leupers is also engaged as an entrepreneur and in turning novel technologies into innovations. He holds several patents on system-on-chip design technologies and has been a co-founder of LISATek (now with Synopsys), Silexica, and Secure Elements. He has served as consultant for various companies, as an expert for the European Commission, and in the management boards of large-scale projects like HiPEAC and UMIC. He is the coordinator of EU projects TETRACOM and TETRAMAX on academia/industry technology Transfer.

Thomas Grass is a postdoctoral researcher at the Institute for Communication Technologies and Embedded Systems at RWTH Aachen University. He received his PhD degree from Universitat Politècnica de Catalunya in 2017. From 2012 to 2017 he was a Junior Researcher at Barcelona Supercomputing Center. In 2011 he received his Dipl.-Ing. Degree from TU Kaiserslautern. His research interests include techniques for performance analysis of parallel computer systems and design methods for future parallel systems. Currently, he is working in the field of Hybrid Prototyping, a technique combining the flexibility of architectural simulation with the speed and accuracy of FPGA prototyping.

Farhad is working as a Postdoctoral Research Fellow at Institute for Communication Technologies and Embedded Systems, RWTH Aachen University Germany. He did his PhD from Indian Institute of Science, Bangalore where he defended his thesis on April 15, 2016. After completing PhD, he spent 10 months at Hardware and Embedded Systems Lab, NTU, Singapore and 1 year at Research and Technology Centre, Robert Bosch. His research interests are secure computer architectures, algorithm-architecture co-design, numerical linear algebra.

Avi Mendelson is a professor in the CS and EE departments Technion, Israel, and a member of the TCE (Technion Computer Engineering center). He earned his BSC and MSC degrees from the CS department, Technion, and got his PhD from University of Massachusetts at Amherst (UMASS).

Prof. Avi Mendelson has a blend of industrial and academic experience. As part of his industrial role, he spent 11 years in Intel, where he served as a senior architect and Principle engineer in the Mobile Computer Architecture Group, in Haifa. As part of this role he was in charge of the CMP definition and architecture of the Core Due 2. (the first intel’s CMP chip). He also served 4 years in Microsoft R&D center where he managed the Academic collaborations. Major part of his work in Microsoft was focused on student innovations and out-of-the-box usages of the cloud.

His research interests span over different areas such as Computer architecture, Operating systems, Power management, reliability, fault-tolerance, cloud computing, HPC and GPGPU including the use of “small devices” for medical purposes.

Shahar Kvatinsky is an assistant professor at the Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion – Israel Institute of Technology.

He received the B.Sc. degree in computer engineering and applied physics and an MBA degree in 2009 and 2010, respectively, both from the Hebrew University of Jerusalem, and the Ph.D. degree in electrical engineering from the Technion – Israel Institute of Technology in 2014.

From 2006 to 2009 he was with Intel as a circuit designer and was a post-doctoral research fellow at Stanford University from 2014 to 2015. Kvatinsky is an editor in Microelectronics Journal and has been the recipient of the 2015 IEEE Guillemin-Cauer Best Paper Award, 2015 Best Paper of Computer Architecture Letters, Viterbi Fellowship, Jacobs Fellowship, ERC starting grant, the 2017 Pazy Memorial Award, the 2014 and 2017 Hershel Rich Technion Innovation Awards, 2013 Sanford Kaplan Prize for Creative Management in High Tech, 2010 Benin prize, and six Technion excellence teaching awards. His current research is focused on circuits and architectures with emerging memory technologies and design of energy efficient architectures.

Mark Silberstein is an Assistant Professor at the Technion Electric Engineering department working on the design and implementation of new generation of computer systems with computational and I/O accelerators, and trusted execution environments.

Professor Michael O'Boyle is internationally known for his ground breaking working in iterative compilation. This technology is now available in mainstream compilers. He has since pioneered incorporating machine learning into compilation, automating the design and construction of optimizing technology which has led to the release of MilePost GCC, the world's first open-source machine learning compiler.

He is a founding member of the High Performance and Embedded Architectures and Compilation Network of Excellence (NoE), the only European NoE in the area. Since 2005, he has been the European leader in HiPEAC's compiler research and development activity. He has been awarded 2 fellowships and 5 international visiting positions including a professorship at Stanford and an UK EPSRC Advanced Research Fellowship. He has published over 75 papers in international journals and conferences. He was the first to integrate machine learning in to dynamic compilation, auto-parallelization, feature generation and adaptive hardware. His recent work on streaming parallelism won the best paper and presentation awards at PACT this year. He is one of only a handful of Europeans to have published in the premier conferences in computer architecture: MICRO and HPCA and one of an even smaller number to have published at the top compilation conferences PLDI, OOPSLA and CGO. He has been a member on more than 50 PCs for every international conferences in his area and is the first ever European Program Chair for ACM CGO (Code Generation and Optimization) 2011, the premier conference for adaptive compilation.

Vijay Nagarajan is a Reader (Associate Professor) at the University of Edinburgh. His research interests span computer architecture and compilers, with a focus on memory consistency models and cache coherence protocols. Vijay received his PhD from University of California, Riverside and MS from University of Arizona. He is a recipient of Intel Early Career Faculty Award and a best-paper award at PACT.

Boris Grot is an Assistant Professor in the School of Informatics at the University of Edinburgh. His research seeks to address efficiency bottlenecks and capability shortcomings of processing platforms for big data. His work on scaling on-chip interconnection networks to thousands of cores was selected as an IEEE Micro Top Pick. He is a Google Faculty Research Award recipient for 2014. Boris Grot has a PhD in Computer Science from The University of Texas at Austin.

Dr Franke's interests are in software transformation, mostly for performance optimisation and parallelisation, but also include various techniques to e.g. reduce code size for embedded processors. He is interested in how to incorporate dynamic information in program analysis. This research has a number of applications, for example to drive better code optimisations applied by a compiler, to enable more aggressive parallelisation of sequential legacy code or to improve performance of just-in-time compilers in dynamic binary translators (also known as instruction set simulators or emulators).

Dr Andy Nisbet is a senior researcher at the University of Manchester working on low-power virtualization for many-cores on ARM architectures. He was previously an Assistant Professor at Trinity College Dublin, where he was principal investigator on 3 nationally funded grants, one Marie-Curie Intra-European Fellowship and collaborator on two further national grants, followed by an Associate Professor position at MMU, UK. He has made contributions in iterative feedback directed compilation, run-time systems, parallel applications development and optimization, GPUs, and FPGAs using high-level hardware description languages. He has published over 60 refereed publications during his career. He has extensive experience of ARMv7 and ARMv8 architectures from work on the PAMELA project concerning profiling and performance understanding in managed runtimes and porting the Maxine Research JVM to ARM. He is currently investigating the use of BCC/eBPF for performance understanding of native and managed applications.

At the University of Manchester, Dirk Koch's group works on run-time reconfigurable systems based on FPGAs ranging from embedded systems to HPC. He developed techniques and tools for self-adaptive distributed embedded control systems based on FPGAs. Current research projects include database acceleration using FPGAs-based stream processing, HPC and exascale computing, as well as reconfigurable instruction set extensions for CPUs. Furthermore, in the FORTE project he is exploring how memristors can be used for building new kinds of analogue, digital and mixed-signal reconfigurable devices.

Dirk is author of the book "Partial Reconfiguration on FPGAs" and a co-editor of the book "FPGAs for Software Programmers" and his group is developing and maintaining the GoAhead framework that provides unique capabilities for building run-time reconfigurable systems.

Dr Antoniu Pop is a Lecturer in the Advanced Processor Technologies group, School of Computer Science, at the University of Manchester. Since 2014, Antoniu holds a Royal Academy of Engineering University Research Fellowship investigating data-centric solutions to the many-core revolution. He conducts research on multiple aspects of parallel software including programming languages, program analysis, data-flow models of computation and compiler and runtime optimizations for parallel and high-performance computer systems.

Antoniu is the lead designer of the OpenStream programming language (http://openstream.info), which he first started to work on first during his PhD at MINES ParisTech, then as a post-doc at Inria and Ecole Normale Superieure in Paris. He has contributed to multiple EU projects (FP6 ACOTES, FP7 TERAFLUX, FP7 PHARAON), investigating data-flow programming models for many-core architectures. In 2005-2007 he contributed to the design and implementation of the ARMI runtime system for STAPL, a partitioned global address space programming model.

He received an MSc degree École Nationale Supérieure d'Informatique et Mathématiques Appliquées de Grenoble in 2004 and his PhD from MINES ParisTech in 2011.

Martin Schulz is a Full Professor at the Technische Universit채t M체nchen (TUM), which he joined in 2017. Prior to that, he held positions at the Center for Applied Scientific Computing (CASC) at Lawrence Livermore National Laboratory (LLNL) and Cornell University. He earned his Doctorate in Computer Science in 2001 from TUM and a Master of Science in Computer Science from UIUC. Martin has published over 200 peer-reviewed papers and currently serves as the chair of the MPI Forum, the standardization body for the Message Passing Interface. His research interests include parallel and distributed architectures and applications; performance monitoring, modeling and analysis; memory system optimization; parallel programming paradigms; tool support for parallel programming; power-aware parallel computing; and fault tolerance at the application and system level. Martin was a recipient of the IEEE/ACM Gordon Bell Award in 2006 and an R&D 100 award in 2011.

Carsten Trinitis received his Ph.D. in Electrical Engineering in 1998 from TUM, working on a parallel automatic optimisation system for electrostatic field simulation. After working in industry, he returned to TUM in 2001, where he now holds a position as senior scientist and is heading the research group on parallel and distributed computer architectures. From 2002 to 2010, he was also an assistant professor for history of science at Universität der Bundeswehr München, Germany. From 2010 to 2014, Carsten was full Professor of Distributed Computing at the University of Bedfordshire, United Kingdom.

Carsten is elected member of Gesellschaft für Informatik (GI)'s board of directors and GI liaison lecturer at TU Munich. In 2016 he was re-elected to serve for another three years in GI's board of directors.

His research interests comprise high performance computer architectures, microprocessor architectures, multi- and many-core architectures as well as the adaptation of numerical simulation codes to these architectures.

Dimitris Gizopoulos is Professor at the Department of Informatics and Telecommunications, University of Athens where he leads the Computer Architecture Laboratory. His research focuses on the dependability, the performance and the energy of computer architectures (built around CPUs, GPUs and other accelerators) for high-performance and embedded computing. Gizopoulos has published more than 170 papers in peer reviewed transactions, journals and conference proceedings, holds patents in microprocessor error detection and is author of one book and editor of three books in dependable computing. He currently serves as Associate Editor for the IEEE Transactions on Computers (TC), IEEE Transactions on Sustainable Computing (TSUSC), and Springer’s JETTA and previously he served as Associate Editor for IEEE Transactions on VLSI Systems and IEEE Design & Test of Computers Magazine. He also served as guest editor for several special issues in IEEE Transactions and Magazines and as member of the Steering, Organizing and Program Committees of several IEEE and ACM conferences. Gizopoulos is a Fellow of IEEE (class of 2013) for his contributions to microprocessor architectures error detection, a Golden Core Member of IEEE Computer Society, and a Senior Member of the ACM. He is member of the HiPEAC and was Vice Chair of the ESF-funded MEDIAN COST Action. His research group activities are currently funded by national resources, the EU (H2020 and FP7 frameworks) as well as the industry (including Cisco, AMD, IBM, ABB, Bosch).

Αntonios Paschalis is Professor at the Department of Informatics and Telecommunications of the National and Kapodistrian University of Athens (NKUA), Director of the Digital Systems & Computer Architecture Laboratory (DSCAL), Academic Member of the Steering Committee of the Hellenic innovation ecosystem in the field of space technologies and applications (si-Cluster), Member of the Board of Hellenic Space Agency (HAS) and Chairman of the Department of Informatics and Telecommunications of the NKUA.

Prof. Paschalis is the local instrument manager of the space technology team that has participated since 2009 in all phases of ESA space mission PROBA-3. He has involved in the development of high-performance hardware accelerators for all data, 2D and 3D (hyperspectral) image compression algorithms, authentication and encryption, and channel coding that satisfies the CCSDS space standards. He participates in the development of the next generation high-performance space data system in collaboration with AIRBUS DS and the German Space Centre DLR. Prof. Paschalis was born in 1960, he received the B.Sc. degree in Physics in 1982, the M.Sc. degree in Electronic Automation and the Ph.D. in Dependable Computers, under scholarship from the NCSR “Demokritos”, in 1987, all from the Department of Physics of the National and Kapodistrian University of Athens. He has more than 30 years of experience in the development of fault-tolerant systems, 20 years of experience in self-testing of VLSI circuits and Systems on Chip and 8 years of experience in the design and architecture of high-performance on-board payload data processing units for space applications. He has published more than 150 scientific publications, he is co-author of a book and he holds a US patent. Ηe has supervised 7 graduated Ph.D. students, 5 of them are in Academia. Currently, there are more than 2,100 citations that refer to his published material and his h-index is 27.

Prof. Dr. Theo Ungerer is a Full Professor of Computer Science at the University of Augsburg, Germany, and Head of the Chair of Systems and Networking. Prior to his appointment to University of Augsburg, he was a professor at the Computer Science Department of Technical University of Karlsruhe, leading research in general and embedded processor architectures and embedded system software. Prof. Ungerer is a founding member of the EC network of excellence HiPEAC (High Performance Embedded Architectures and Compilers). He serves on the Editorial Boards of the International Journal of Parallel Programming (IJPP) and the Journal of Personal and Ubiquitous Computing (PUC), in the Steering Committees of the ARCS conference and the Autonomic and Trusted Computing (ATC) conference series. He was Programme Chair of ARCS 2003 and HiPEAC 2012, General Chair of ARCS 2004, 2008 and ATC 2006, Publications Chair of several HiPEAC conferences, and serves in many Programme Committees.

Yiannakis Sazeides is an Associate Professor at the University of Cyprus. He was awarded a PhD from the University of Wisconsin-Madison in 1999. He worked at Compaq and Intel towards the development and design of high performance processors. His research interests lie in the area of Computer Architecture with particular emphasis on reliability, data center modelling, memory hierarchy, and analysis of dynamic program behavior.

Chrysostomos Nicopoulos is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Cyprus. Dr. Nicopoulos received the B.S. and Ph.D. degrees in Electrical Engineering (specializing in Computer Engineering) from the Pennsylvania State University, USA, in 2003 and 2007, respectively. His Ph.D. dissertation, titled: “Network-on-Chip Architectures: A Holistic Design Exploration,” received the 2008 Outstanding Dissertation Award in the area of "New directions in logic and system design" by the European Design and Automation Association (EDAA). From 2007 to 2008, he worked as a post-doctoral research associate in the Processor Architecture Laboratory at the École Polytechnique Fédérale de Lausanne (EPFL), Switzerland. He currently leads the multicore Computer Architecture Laboratory (multiCAL) in the Department of Electrical and Computer Engineering at the University of Cyprus. His research interests lie in the areas of Networks-on-Chip (NoC), computer architecture, and multi-/many-core microprocessor and computer system design.

Prof. Dr.-Ing. Dietmar Fey is a Professor of Computer Science at FAU where he leads the Chair for Computer Architecture since 2009. His research interests are in Parallel Computer Architectures and Embedded Systems, Parallel Programming Environments, methods and tools for Emulation of Heterogeneous Hardware Architectures, Smart Sensors and Memristive Computing. He was involved in the European projects “Interchip Optical Communications and Photonic PCBs for next generation OBP” funded by ESA and in the H2020 HPC project AllScale. Furthermore he was involved in several national and international research projects and initiatives on parallel and embedded computing, e.g. the nationwide Priority Program “Organic Computing” funded by German Research Foundation (DFG) and he was one of the PIs in the DFG funded Ph.D. student elite Research Training Group on “Heterogeneous Image Systems”. He was also project leader in joint projects with industrial partners on Grid and Cloud Computing (OptinumGrid, part of the German D-Grid, and Cloud4Eng, part of the nationwide program Trusted Cloud) funded by the German Ministries for Education and Research and for Economic Affairs and Energy. He has published over 200 conference articles including 3 books, and about 35 papers in journals. He is a member of HiPEAC (European Network of Excellence on High Performance and Embedded Architecture and Compilation) and a contributor of the HiPEAC roadmap, author of the Eurolab4HPC report “Disruptive Technologies for years 2020-2030”, and he is a member of the EU Cost Action 1401 “Memristors Devices, Models, Circuits, Systems and Applications”.

Johannes Hofmann holds a master's degree in Computer Science and is a PhD student at the Chair for Computer Architecture of the University of Erlangen-Nuremberg. His research focus is on performance modelling and engineering for contemporary multi- and many-core processors, as well as developing models and best practices for energy-efficienct computing.

Gerhard Wellein holds a PhD in Theoretical Physics from the University of Bayreuth and is a Professor for High Performance Computing at the Department for Computer Science at University of Erlangen-Nuremberg. He heads the HPC group at Erlangen Regional Computing Center (RRZE) and he is vice chairman of the steering committee of the Gauß Center for supercomputing. His research interests include techniques, models and tools for performance engineering, hardware-specific optimization, novel parallelization approaches as well as hardware-efficient sparse eigenvalue solvers and high-performance lattice Boltzmann methods. He has also a long track record of teaching HPC techniques to students and scientists.

Erik Hagersten has moved between industry and academia seven times and is currently a chaired professor in Computer Architecture at Uppsala University in Sweden. Before moving to Sweden he was the chief architect for the high-end server division at Sun Microsystems. His resent startup Acumem AB developing performance analysis tools for the memory hierarchy and was acquired by Rogue Wave Inc. in 2010.

Erik’s research interests focus on ultra-fast performance modeling techniques as well as the software and hardware optimizations they enable. In addition, he has a hard time resisting “traditional” architecture research since it is so much fun. In his prior research, he introduced the Cache-Only Memory Architecture and its brain-dead acronym COMA.

He is a member of the Swedish Royal Academy of Science and Engineering and is this year’s recipient of Uppsala University’s most prestigious research award (Björkénska).

David Black-Schaffer is an associate professor in the computer architecture research group at Uppsala University, Sweden. His research focus is on runtime performance, in particular low-overhead measurement and modeling, as well as power, both micro-architectural and runtime, and heterogeneous scheduling. Before coming to Uppsala he obtained a PhD degree from Stanford University working on power-efficient embedded systems architectures and spent time at Apple developing the OpenCL standard.

Alexandra Jimborean is Assistant Professor at Uppsala University since 2015. She obtained her PhD from the University of Strasbourg, France in 2012, was awarded the Anita Borg Memorial Scholarship offered by Google in recognition of excellent research, along with other 30 distinctions, awards and grants. Her research focuses on compile-time and run-time code analysis and optimization for performance and energy efficiency and on software-hardware co-designs.