Upcoming

Start: March 12, 2019
End: March 13, 2019

Eurolab4HPC Workshop on Embedded Multicore Programming

This event, organized by the Eurolab4HPC project, in cooperation with HiPEAC and TETRAMAX, will address multicore programming issues within an informal and interactive workshop set-up.

The shift from single-core to multicore hardware platforms affects virtually all computing domains today. Multicore CPUs and heterogeneous system-on-chip platforms promise to meet skyrocketing application performance demands at moderate power and energy consumption. Yet, product quality requires more than powerful silicon chips. It is the software that makes the real difference. Suboptimal utilization of multicore hardware resources by the program code running on them is a bottleneck in many systems today. The times of simple von Neumann style sequential programming are gone – probably forever. Yet, manual parallelization of legacy software for complex multicores is extremely costly, risky, tedious, and error-prone. With exponentially growing complexity in both application software and hardware platforms, the challenges are here to stay.

Topics of interest

  • Multicore programming models
  • Target hardware architecture modeling
  • Sequential code parallelization
  • Software task mapping
  • Parallel target code generation
  • Performance/power co-optimization
  • Empirical results for specific application domains

Contents

Day 1 (March 12):

  • 12:30-13:00 Welcome and snacks
  • 13:00-14:30 Session 1: Selected technical presentations
  • 14:30-15:00 Coffee break
  • 15:00-16:30 Session 2: Selected technical presentations (cont.)
  • 18:30-21:00 Social dinner

Day 2 (March 13):

  • 09:30-10:00 Session 3: Keynote by M. Odendahl (CEO, Silexica)
  • 10:00-11:00 Session 4: Silexica technology presentation and demo
  • 11:00-11:30 Coffee break
  • 11:30-13:00 Session 5: Silexica technology presentation and demo (cont.)
  • 13:00-13:30 Wrap-up discussions and farewell buffet

Registration

Registrations are limited and will be handled on a first-come, first-served basis. Participation is free of charge. To confirm your participation, please send your name, affiliation, Email address and phone number to Vicky.Wandels@ugent.be . Please also indicate whether you would like to contribute a presentation (approx. 20 minutes) yourself. For any questions, please contact: leupers@ice.rwth-aachen.de

Venue

RWTH Aachen University
ICT cubes, Seminar room 002
Kopernikusstrasse 16
52074 Aachen, Germany

Organizing Committee

Rainer Leupers, RWTH Aachen University
Per Stenström, Chalmers University
Thomas Grass, RWTH Aachen University
Farhad Merchant, RWTH Aachen University