One of the missions of Eurolab4HPC is to bring together researchers, industry and users for the development and the use of open source hardware and software creating a community to work on long-term projects. We believe that open source projects provide a natural forum for testing ideas and discovering innovation opportunities thereby promoting promote entrepreneurship, fostering industry take-up, and providing an avenue to train more experts in Exascale hardware and software.
This page will provide links to major Open Source projects related to the HPC domain and announce open source activities of Eurolab4HPC.
Contact us if you have an Open Source project that you want to have listed here.
Automatic speculative POLyhedral Loop Optimizer
APOLLO is a compiler framework dedicated to automatic, dynamic and speculative parallelization and optimization of programs' loop nests. It is developed at Inria in the CAMUS Team and at the University of Strasbourg in the CNRS laboratory ICube, France. This framework allows a user to mark in a C/C++ source code some nested loops of any kind (for, while or do-while loops) in order to be handled by a speculative parallelization process, to take advantage of the underlying multi-core processor architecture. The framework is composed of two main parts. First, extensions to the CLANG-LLVM compiler are devoted to prepare the program for being handled by the runtime system.
A Benchmark Suite for Cloud Services
CloudSuite is a benchmark suite for cloud services. The third release consists of eight applications that have been selected based on their popularity in today's datacenters. The benchmarks are based on real-world software stacks and represent real-world setups.
A package manager and a set of build tools for FPGA/ASIC development
FuseSoC allows users describe their cores in a mostly tool-agnostic way and lets them depend on each other to build up larger systems from a library of cores. It also allows a design to target different tools, often with only minimal or no changes to the core description. Together, these benefits allow users to rapidly create designs from existing building blocks and move between different simulators or hardware targets. Today, there exists many hundreds of FuseSoC-compatible cores, it has support for 15 different EDA tools and many projects are looking at moving away from having a custom build system to use FuseSoC instead.
FuseSoc is licensed under GPLv3. This means that the FuseSoC code base is guaranteed to be kept as open source, while users of FuseSoC are allowed to keep their core description files and resulting EDA project files open source or proprietary as they wish.
Enabling Intelligence in Battery Powered IoT Devices
GreenWaves Technologies develops IoT Application Processors based on Open Source IP blocks enabling content understanding applications on embedded, battery-operated devices with unmatched energy efficiency. Our first product is GAP8. GAP8 provides an ultra-low power computing solution for edge devices carrying out inference from multiple, content rich sources such as images, sounds and motions. GAP8 can be used in a variety of different applications and industries.
A fully open-sourced, Linux-capable, System-on-a-Chip
lowRISC is creating a fully open-sourced, Linux-capable, RISC-V-based SoC, that can be used either directly or as the basis for a custom design. We aim to complete our SoC design this year. Our open-source SoC (System-on-a-Chip) designs will be based on the 64-bit RISC-V instruction set architecture. Volume silicon manufacture is planned as is a low-cost development board. lowRISC is a not-for-profit organisation working closely with the University of Cambridge and the open-source commu
Open Tiled Manycore System-on-Chip
OpTiMSoC is an open-source framework that allows you to build your own manycore System-on-Chip by connecting tiles like processors and memories through a Network-on-Chip. The goal of OpTiMSoC is to create a freely available, open source framework for research on manycore System-on-Chip. By providing basic blocks, such as a Network-on-Chip in different configurations, processing elements (CPU cores), hardware accelerators, and I/O modules creating a new SoC is a matter of plugging the different components together. The resulting hardware can then be simulated on a PC or synthesized and run on an FPGA.
On top of the hardware components, a basic runtime system as well as a trace-based debug and diagnosis infrastructure enable rapid prototyping.
PULP is an open-source multi-core computing platform part of the of the ongoing collaboration between ETH Zurich and the University of Bologna - started in 2013. The PULP architecture targets IoT end-node applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors.
PULP consists of an advanced microcontroller architecture representing a significant step ahead in terms of completeness and complexity with respect to PULPino, taking care of autonomous I/O, advanced data pre-processing, external interrupts, and including a tightly-coupled cluster of processors to which compute-intensive kernels can be offloaded from a main processor.
Quick & Flexible Rack-Scale Computer Architecture Simulator