Date: Aug. 23, 2018

The RISC-V Session at HiPEAC Spring CSW in Göteborg

EUROLAB4HPC organized a Thematic Session on RISC-V in the spring edition of HiPEAC Computing System Week in Göteborg, Sweden on May 22, 2018. The aim of the session was to help creating EUROLAB4HPC and HiPEAC based activities and working groups that will research, innovate and create open source hardware (and tools) based on RISCV. It featured a tutorial on RISC-V offered by Luca Benini, ETH. This was followed by three enlightening invited talks on security aspects by Carles Hernandez from Barcelona Supercomputing Center, on LLVM technology by Alex Bradbury from Cambridge University and on RISC-V memory models by Per Stenström, Chalmers. This was followed by an interesting panel discussion with the theme of how to align and work together to form a strong RISC-V community in Europe led by Avi Mendelson, Technion.

RISC-V is a free and open Instruction-Set Architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.RISC-V has been chosen as one of the candidates for accelerator designs in the European Processor Initiative (EPI) that will co-design, develop and bring on the market a European low-power microprocessor. The EPI technology, with drastically better performance and power, is one of the core elements needed for the development of the European Exascale machine.